1. Field of the Invention
The present invention relates to a power converter for an AC Motor Vehicle generator utilizing MOS power transistors and which is applicable to an alternator capable of generating power by turning kinetic energy during braking of the vehicle into electrical power and to the main drive motor of an electric car, as well as to a so-called alternator driven by an engine.
2. Related Art
There is known an AC generator for motor vehicles which includes a three-phase full-wave rectifier as a power converter having high-side semiconductor power elements and low-side semiconductor power elements for individually connecting each end of a three-phase armature winding of the AC generator, respectively, with a high potential end and a low potential end of a battery, and a controller for synchronously connecting/disconnecting each semiconductor power element and in which the three-phase full-wave rectifier converts a generated voltage of the three-phase armature winding into a DC voltage to feed to the battery. Japanese Patent Laid-open No. 4-138030, for example, discloses using a MOS power transistor as the semiconductor power element.
That is, an N-channel MOS power transistor type three-phase full-wave rectifier disclosed in the above-mentioned publication has three high-side MOS power transistors that connect each end of a three-phase armature winding of an AC generator for motor vehicles with a high potential end of a battery and three low-side MOS power transistors that connect each end of the three-phase armature winding with a low potential end of the battery.
For the MOS power transistor of this type, it is common to adopt a vertical MOS power transistor structure in which an N-type silicon substrate is formed as one main electrode of the MOS power transistor and an N.sup.+ -type region is formed on the surface of a P-type well region formed on the surface of the chip as another main electrode to maintain its withstanding voltage and to reduce ON resistance.
Further, while a parallel field coil scheme in which a field coil, which is connected in parallel with a three-phase full-wave rectifier, is used as a DC magnetizing means of a magnet core of an AC generator for motor vehicles and a magneto scheme whose structure and control are relatively simple are generally used, the present applicant has proposed a magneto scheme combined with a serial field coil in which a three-phase full-wave rectifier and exciting coil are connected in series to enhance a magnetic field flux as another method.
Because the three-phase full-wave rectifier using the MOS power transistors has a structure in which a parasitic diode which functions as a PN junction diode of the conventional three-phase full-wave rectifier and the MOS power transistor are connected in parallel, there is a possibility that a power loss equivalent to a voltage drop of the junction diode in the forward direction may be reduced as compared to the conventional three-phase full-wave rectifier using silicon diodes.
However, it was found from the analysis made by the present inventors that the above-mentioned MOS power transistor type three-phase full-wave rectifier has the following problems.
Because an accumulated amount of magnetic energy in the three-phase armature winding and field coil is large in the AC generator for motor vehicles, a withstanding voltage of each semiconductor power element of the three-phase full-wave rectifier has to be set to be more than a battery voltage, i.e., more than 20 times the output rectified voltage of the three-phase full-wave rectifier, e.g., about 300 V, as a measure to deal with such possible accidents as where it is instantaneously released as a voltage when an output terminal of the generator comes off, for example.
In an enhancement type MOS power transistor, a parasitic diode Ds on the side connected to the source is produced between a well region and source region and a parasitic diode Dd on the side connected to the drain is produced between the well region and drain electrode in principle. In the N-channel MOS power transistor, while the P-type well region is normally connected with a source electrode or a drain electrode in order to give a potential to the P-type well region, the P-type well region and the drain electrode have to be connected in the three-phase full-wave rectifier for the AC generator for motor vehicles (i.e., the parasitic diode Dd on the side connected to the drain is short-circuited).
That is, if the P-type well region and source electrode are connected and the parasitic diode Ds on the side connected to the source is short-circuited in the three-phase full-wave rectifier for the AC generator for motor vehicles, a reverse current (a diode forward direction current) flows through the parasitic diode Dd on the side connected to the drain when a generated voltage connected to the drain electrode of the high-side MOS power transistor drops to less than the battery voltage. Similarly, a reverse current (a diode forward direction current) flows through the parasitic diode Dd on the side connected to the drain if a generated voltage connected to the source electrode of the low-side MOS power transistor rises above a potential (ground potential) voltage at the low potential end of the battery. Accordingly, the P well region has to be connected to the drain electrode in order to block the reverse current flowing through the parasitic diode Dd by the parasitic diode Ds on the side connected to the source. The same applies to a P-channel MOS power transistor as well.
However, in the conventional MOS power transistor structure shown in FIG. 7 or 8, a P-type well region 103 and N.sup.+ -type region 104 on the surface Of the region 103 cannot but be short-circuited to extend a PN junction depletion layer 107 between the P-type well region 103 and an N-type epitaxial voltage withstanding layer 105 toward the N-type voltage withstanding layer 105 to earn a withstanding voltage during OFF.
That is, when the three-phase full-wave rectifier for the AC generator for motor vehicles is constructed from the above-mentioned MOS power transistor structure, an N.sup.+ -type substrate 106 must be set as a source region and the N.sup.+ -type region 104 must be set as a drain region. By doing so, however, a large source parasitic resistance Rs of the N-type voltage withstanding layer 105 is connected between a substantial source end S' and the source electrode in series.
A drain saturation current Idsat of the MOS transistor may be expressed as follows; ##EQU1## wherein a threshold voltage Vt is ignored for simplification and where K is a proportional constant, .DELTA.Vgs is a voltage between source and gate (Vg-Vs), Vg is a gate voltage, Vs' =Vs+Idsat.multidot.Rs is a potential at the substantial source end S'.
That is, for the drain saturation current (maximum current when a predetermined gate voltage is applied) Idsat, it is equivalent to that the gate voltage Vg equivalent to Idsat.multidot.Rs has dropped. Changes of the threshold voltage Vt due to a substrate effect is also ignored.
For example, when a gate voltage is +20 V, source (battery) potential is +12 V, current is 100 A and source parasitic resistance Rs is 0.05 .OMEGA., an actual source potential Vs' turns out to be 17 V, which indicates that a channel current drops to 9/64 as compared to a case when Rs is 0. That is, it can be seen that the channel current is reduced extremely by the minor increase of the source parasitic resistance Rs. Hereinafter, this current reducing effect, i.e. a channel resistance increasing effect, will be referred to as a source resistance feedback effect.
While the above expression illustrates the drain current saturation region, a drain non-saturation current is also reduced by the increase of Rs in a non-saturation region. Such a reduction of the drain current implies that the increase of the channel resistance and the increase of the source parasitic resistance Rs causes a power loss due to the increase of the channel resistance. A power loss is caused by itself, so that it can be seen that a considerable amount of power is lost and heat is generated as a whole.
Although it is possible to thin the N-type voltage withstanding layer 105 in order to reduce the source parasitic resistance Rs, it is difficult to thin the N-type voltage withstanding layer 105 since the AC generator for motor vehicles requires a high withstanding voltage of 300 V.
That is, a yield field strength of a silicon is about 30 V/.mu.min a conventional silicon MOS power transistor and if the above-mentioned 300 V of withstanding voltage is to be earned only by the N-type voltage withstanding layer 105, its thickness has to be 10 .mu.m assuming that the field strength within the N-type voltage withstanding layer 105 is constant. Actually, because the field strength is concentrated near the PN junction, the thickness has to be more than about 20 .mu.m and its impurity concentration has to be less than about 1.times.10.sup.15 atoms/cm.sup.3 if the field strength near the PN junction is about 30 V/.mu.m and the N-type voltage withstanding layer 105 is to bear the 300 V of withstanding voltage. The formation of the N-type voltage withstanding layer 105 having such thickness and impurity concentration to maintain the withstanding voltage causes increases in the source parasitic resistance Rs and the loss of the resistance due to that and the reduction of the drain current (the considerable increase of the channel resistance) as described above. As a result, the MOS power transistor type three-phase full-wave rectifier in the above-mentioned publication has problems that it is theoretically impossible for it to exceed the PN junction diode type three-phase full-wave rectifier for the use of the AC generator for motor vehicles (i.e. in the reactance load field) and that its structure and control are complex.
On the other hand, it is conceivable to constitute the N.sup.+ -type region 104 as the source electrode and the N.sup.+ -type substrate 106 as the drain electrode and to short-circuit the P-type well region 103 and the N.sup.+ -type substrate 106 in the MOS power transistor structure shown in FIG. 7 or 8 described above. However, it is extremely difficult to maintain 300 V of withstanding voltage between the N.sup.+ -type region 104 constituting the source electrode and the P-type well region 103 and to maintain the withstanding voltage between the gate electrode and the P-type well region 107 and the N.sup.+ -type region 104.